1. Field of the Invention
This disclosure relates to digital memory. More particularly, this disclosure provides a reduced capacitance memory system and device, and further provides a method for operating a memory system to reduce capacitance and transmission line stub length within the system.
2. Description of the Related Art
As computers and their central processing units ("CPUs") become capable of executing instructions more rapidly, this ability carries with it a need for increased memory size and speed, and also bus size. The need has given rise to much design effort directed toward optimizing current and future memory device designs to provide quick memory response. Commonly-recognized current examples of memory devices include dynamic random access memories ("DRAMs"), read only memories ("ROMs") and static random access memories ("SRAMs"), as well as mechanical and optical devices, such as CD-ROMs.
In performing a typical data read operation, a memory controller (usually the CPU or, in larger systems, a dedicated memory controller) sends a read command to a particular memory chip. This command is propagated to the chip along one or more lines of a command bus. When received by the particular chip, the command causes the chip to locate and direct an output from its internal memory array onto a data bus, as a return data signal intended for the memory controller. The output then propagates along the data bus, which may or may not travel the same route as the command bus. In the example just given, there are three sources of time delay, including the propagation time of a read command from the controller to the chip, the time required for the chip to power its internal registers and to channel the proper output onto the data bus, and the time required for propagation of the output back to the controller.
Similarly, in performing a typical data write operation, the memory controller sends a write command to a particular memory chip along with the data to be written. This command is propagated to the chip along one or more lines of a command bus, while the data is propagated to the chip along one or more line of a data bus. When received by the particular chip, the command causes the chip to channel the data from the data bus to the specified location of its internal memory array. The data propagating along the data bus may or may not travel the same route as the command propagating along the command bus. In the example just given, there are three sources of time delay, including the propagation time of a write command from the controller to the chip, the time required for propagation of the data from the controller, and the time required for the chip to power its internal registers and to channel the data from the data bus.
Typically, design efforts have focused primarily on improving internal routing and processing of instructions within memory chips. These design efforts, however, while continually providing more responsive memory devices, do not address the primary cause of propagation delay along the data bus, inherent capacitance of the data bus. As a result, many systems are sending data over the data bus at rates far lower than the operating speeds of the CPUs.
The problem of inherent capacitance is further explained with reference to FIGS. 1 and 2. FIG. 1 illustrates a data path within a typical memory system 1. The data path includes a memory controller 2, a motherboard 3, memory chips 4, memory modules 5, and a data bus 6. The data bus 6 includes board trace portions 7, module trace portions 8, connectors 9, and termination 10. The memory controller is affixed to the motherboard and is electrically connected to the memory chips via the data bus. The memory chips are affixed to the memory modules. The board trace portion of the data bus is affixed to the motherboard and the module trace portion of the data bus is affixed to the memory modules. The board trace portion has a termination 10. The connectors 9 electrically connect the board trace portions to the module trace portions and mechanically affix the memory modules to the motherboard.
FIG. 2 depicts the electrical equivalent 11 of the typical data path shown in FIG. 1. For ease of reference, each electrical equivalent in FIG. 2 that represents a component shown in FIG. 1 is labeled with the reference numeral of the represented component with the suffix "A". It should be noted that the board trace portion 7A is made up of inductive and capacitive elements which together behave as a transmission line 12 having a set of impedance and transmission delay characteristics. Similarly, each of the module trace portions 8A are made up of inductive and capacitive elements which together behave as transmission lines 13, each having its own set of impedance and transmission delay characteristics.
When properly terminated with a resistor 10A, the board trace portion 7A acts as a nearly perfect transmission line (not shown) without inherent capacitance and will not in and of itself limit the operating speed of the memory system. When combined with the module trace portions 8A, however, the module trace portions 13 act as transmission line stubs coming off of the board trace portion 7A. These stubs together have a "comb filter" effect that includes significant signal reflections in the memory system that decreases signal integrity. This "comb filter" effect imposes a load on the data bus and effectively breaks the board trace portion 7A into individual board trace portion transmission lines 13.
The load imposed by the "comb filter" effect limits the maximum transmission speed of data propagation in both the board trace portion 7A and the module trace portions 8A. The "comb filter" effect imposed by the stubs generally increases as the length of each the module trace portions 7A increases. Similarly, the "comb filter" effect imposed by the stubs generally decreases as the length of each of the module trace portions decreases. A second cause of the propagation delays for data signals sent from the memory controller 2A to the memory chips 4A are the inductive element 14 and capacitive element 15 associated with each memory chip. Together, the inductive and capacitive elements impose a capacitive load on the data bus including both the module trace portions 8A and the board trace portion 7A. The load imposed by the "comb filter" effect and the capacitive load imposed by the memory chip elements together form the inherent capacitance load on the memory bus.
Current memory systems attempt to solve the problem of inherent capacitance in the memory bus in several ways. One solution is to provide series resistors on the module trace portion of the data bus in order to electrically separate the module trace portion from the board trace portion of the bus. This technique has been successfully used for frequencies of up to 66 MHZ, but has not been very successful at higher frequencies. Another solution is to provide FET switches on the mother board that break the data bus into sections. For example, a switch multiplexor has been used to separate a set of four memory modules into two electrically independent groups of two modules. This approach creates two smaller memory busses, each presenting less inherent capacitance that the original larger bus. Each of these smaller busses however, still have inherent capacitance load on the data bus and thus have limited signal propagation speed.
In order to keep pace with CPU design and the tendency toward increased computer speed and memory capacity there exists a need for faster memory systems. In particular, there exists a need for a memory system that minimizes the inherent capacitance load on the data bus in order to speed data propagation along the data bus.